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HT68F20 Datasheet(PDF) 119 Page - Holtek Semiconductor Inc |
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HT68F20 Datasheet(HTML) 119 Page - Holtek Semiconductor Inc |
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119 / 210 page  HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Rev.1.00 119 November 3, 2009 CCRA Counter Value Counter Cleared by CCRA CCRA Int. Flag TnAF TnON bit PWM Period set by CCRA Counter Stops if TnO N bit low Count er reset when TnON ret urns high PWM resumes operation - output s remain at same level Time TnBPOL bit TPnB Pin TnBOC = 0 TnPAU bit Resume Paus e CCRB CCRB Int. Flag TnBF TPnB Pin TnBOC = 1 Duty Cycle s et by CCRB Out put Inverts When TnBPOL = 1 TnCCLR = 1; Mode Bits TnA(B)M1, TnA(B)M0 = 10 TnPW M1/TnPWM0 = 00 PWM Mode - Edge Aligned Note: 1. Here TnCCLR = 1 therefore CCRA clears counter and determines PWM period 2. Internal PWM function continues even when TnBIO1, TnBIO0 = 00 or 01 3. CCRA controls TPnB PWM period and CCRB controls TPnB PWM duty |
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