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HT68F20 Datasheet(PDF) 121 Page - Holtek Semiconductor Inc |
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HT68F20 Datasheet(HTML) 121 Page - Holtek Semiconductor Inc |
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121 / 210 page  HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Rev.1.00 121 November 3, 2009 CCRA CCRA Int. Flag TnAF TnON bit PWM Period set by CCRA Time TnBPOL bit Output I nvert s When TnBPO L = 1 TPnB Pin TnBOC = 0 TnPAU bit Resume Pause CCRB CCRB Int. Flag TnBF TPnB Pin TnBOC = 1 Duty Cycle set by CCRB Counter Value Counter Stops if TnON bit low Counter reset when TnON ret urns high TnCCLR = 1; Mode Bits TnA(B)M1, TnA(B)M0 = 10 TnPWM1/TnPWM0 = 11 PWM Mode - Centre Aligned Note: 1. Here TnCCLR = 1 therefore CCRA clears counter and determines PWM period 2. TnPWM1/TnPWM0 = 11 therefore PWM is centre aligned 3. Internal PWM function continues even when TnBIO1, TnBIO0 = 00 or 01 4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty |
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