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ST7571 Datasheet(PDF) 22 Page - Sitronix Technology Co., Ltd. |
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ST7571 Datasheet(HTML) 22 Page - Sitronix Technology Co., Ltd. |
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22 / 76 page  ST7571 Ver 1.5a 22/76 2009/7/21 7.2 DISPLAY DATA RAM (DDRAM) The Display Data RAM stores pixel data for the LCD. It is 129-row by 128-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8 lines and the 17 th page with a single line (DB0 only). Data is written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The LCD controller and MPU interface operate independently, data can be written into RAM at the same time when data is being displayed without flicker on LCD. Page Address Circuit It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 16 is a special RAM area for the icons and display data DB0 is only valid. The page address is set from 0 to 15, and Page 16 is for Icon page. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line Address of icons. Column Address Circuit When set Column Address MSB / LSB instruction is issued, 7-bit (X[7:1]) are set and lowest bit (X0) is set to “0”. The internal column address (X[7:0]) is increased by 1 automatically after each byte of data access (write data). After sequential access twice, the column address (X[7:1]) will point to the next column address. Please refer to Fig. 12. Segment Control Circuit This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the Display Data RAM. SEG Output SEG 0 SEG 1 SEG 2 SEG 3 … SEG 124 SEG 125 SEG 126 SEG 127 Column Address X[7:1] 00H 01H 02H 03H … 7CH 7DH 7EH 7FH Internal column address X[7:0] 00 01 02 03 04 05 06 07 … F8 F9 FA FB FC FD FE FF Display Data (MX=0) 1 1 1 0 0 1 0 0 … 1 1 1 0 0 1 0 0 LCD panel display … Display data (MX=1) 0 0 0 1 1 0 1 1 … 0 0 0 1 1 0 1 1 LCD panel display … Fig. 12 The Relationship between the Column Address and The Segment Outputs |
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