ST7575 datasheet(43/51 Pages) SITRONIX

43 / 51 page

ST7575

Ver 1.3

43/51

2007/09/12

SERIAL INTERFACE (3-Line Interface)

First bit

Last bit

(VDD = 3.3V , Ta =-30~85

°C)

Item

Signal

Symbol

Condition

Min.

Max.

Unit

Serial clock period

tSCYC

120

—

SCLK “H” pulse width

tSHW

—

SCLK “L” pulse width

SCLK

tSLW

—

Data setup time

tSDS

—

Data hold time

SDA

tSDH

—

CSB-SCLK time

tCSS

—

CSB-SCLK time

CSB

tCSH

130

—

(VDD = 2.8V , Ta =-30~85

°C)

Item

Signal

Symbol

Condition

Min.

Max.

Unit

Serial clock period

tSCYC

180

—

SCLK “H” pulse width

tSHW

—

SCLK “L” pulse width

SCLK

tSLW

—

Data setup time

tSDS

—

Data hold time

SDA

tSDH

—

CSB-SCLK time

tCSS

—

CSB-SCLK time

CSB

tCSH

160

—

(VDD = 1.8V , Ta =-30~85

°C)

Item

Signal

Symbol

Condition

Min.

Max.

Unit

Serial clock period

tSCYC

240

—

SCLK “H” pulse width

tSHW

120

—

SCLK “L” pulse width

SCLK

tSLW

120

—

Data setup time

tSDS

—

Data hold time

SDA

tSDH

—

CSB-SCLK time

tCSS

—

CSB-SCLK time

CSB

tCSH

190

—

*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.

*2 All timing is specified using 20% and 80% of VDD1 as the standard.

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