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ST7626 Datasheet(PDF) 21 Page - Sitronix Technology Co., Ltd. |
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ST7626 Datasheet(HTML) 21 Page - Sitronix Technology Co., Ltd. |
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21 / 94 page ![]() ST7626 Ver 1.5 21/94 2007/01/20 7.3 DISPLAY DATA RAM (DDRAM) 7.3.1 DDRAM It is 98 X 68 X 16 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the page address and column address. Since display data from MCU D7 to D0 and D15 to D8 correspond to one or two pixels of RGB, data transfer related restrictions are reduced, realizing the display flexing. The RAM on ST7626 is separated to a block per 4 lines to allow the display system to process data on the block basis. MPU’s read and write operations to and from the RAM are performed via the I/O buffer circuit; Reading of the RAM for the liquid crystal drive is controlled from another separate circuit. Refer to the following memory map for the RAM configuration. Memory Map (When using the Type A 4096 color. 8-bit mode) RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column 0 1 97 P11:0(DATCTL) 97 96 0 P11:1(DATCTL) Color R G B R G B R G B LCD read direction Data Page Block P10:0 (DATCTL) P10:1 (DATCTL) D0_7 D0_6 D0_5 D0_4 D0_3 D0_2 D0_1 D0_0 D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0 D2_7 D2_6 D2_5 D2_4 D2_3 D2_2 D2_1 D2_0 D146_3 D146_2 D146_1 D146_0- D147_7 D147_6 D147_5 D147_4 D147_3 D147_2 D147_1 D147_0 0 67 1 66 2 65 0 3 64 4 63 5 62 6 61 1 7 60 60 7 61 6 62 5 15 63 4 64 3 65 2 66 1 16 67 0 SEGout 0 1 2 3 4 5 291 292 293 |
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