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PIC12F615 Datasheet(PDF) 14 Page - Microchip Technology |
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PIC12F615 Datasheet(HTML) 14 Page - Microchip Technology |
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14 / 212 page  PIC12F609/615/617/12HV609/615 DS41302D-page 14 2010 Microchip Technology Inc. TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 115 01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 115 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 115 03h STATUS IRP(1) RP1(1) RP0 TO PD ZDC C 0001 1xxx 18, 115 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 115 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 115 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 115 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 20, 115 0Ch PIR1 — — — —CMIF — —TMR1IF ---- 0--0 22, 115 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 62, 115 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — 19h VRCON CMVREN — VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 76, 116 1Ah CMCON0 CMON COUT CMOE CMPOL —CMR —CMCH 0000 -0-0 72, 116 1Bh — — — — — 1Ch CMCON1 — — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 73, 116 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — — Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: Read only register. |
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