Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

DM9010BEP Datasheet(PDF) 49 Page - Davicom Semiconductor, Inc.

Part # DM9010BEP
Description  10/100 Mbps Single Chip Ethernet Controller With General Processor Interface
PDF  62 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  DAVICOM [Davicom Semiconductor, Inc.]
Direct Link  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9010BEP Datasheet(HTML) 49 Page - Davicom Semiconductor, Inc.

Back Button DM9010BEP Datasheet HTML 45Page - Davicom Semiconductor, Inc. DM9010BEP Datasheet HTML 46Page - Davicom Semiconductor, Inc. DM9010BEP Datasheet HTML 47Page - Davicom Semiconductor, Inc. DM9010BEP Datasheet HTML 48Page - Davicom Semiconductor, Inc. DM9010BEP Datasheet HTML 49Page - Davicom Semiconductor, Inc. DM9010BEP Datasheet HTML 50Page - Davicom Semiconductor, Inc. DM9010BEP Datasheet HTML 51Page - Davicom Semiconductor, Inc. DM9010BEP Datasheet HTML 52Page - Davicom Semiconductor, Inc. DM9010BEP Datasheet HTML 53Page - Davicom Semiconductor, Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 49 / 62 page
background image
DM9010B
Single Chip Ethernet Controller with General Processor Interface
Preliminary
49
Version: DM9010B--DS-P01
September 5, 2007
10.3 AC Electrical Characteristics & Timing Waveforms
10.3.1 TP Interface
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tTR/F
100TX+/- Differential Rise/Fall Time
3.0
-
5.0
ns
tTM
100TX+/- Differential Rise/Fall Time
Mismatch
0
-
0.5
ns
tTDC
100TX+/- Differential Output Duty Cycle
Distortion
0
-
0.5
ns
tT/T
100TX+/- Differential Output Peak-to-Peak
Jitter
0
-
1.4
ns
XOST
100TX+/- Differential Voltage Overshoot
0
-
5
%
10.3.2 Oscillator/Crystal Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
TCKC
TCKC
39.998
40
40.002
ns
50ppm
TPWH
OSC Pulse Width High
16
20
24
ns
TPWL
OSC Pulse Width Low
16
20
24
ns
10.3.3 Power On Reset Timing
PWRST#
Strap pins
T2
T1
EECS
T3
T4
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
T1
PWRST# Low Period
1
-
-
ms
-
T2
Strap pin hold time with PWRST#
40
-
-
ns
-
T3
PWRST# high to EECS high
-
11.31
-
us
T4
PWRST# high to EECS burst end
-
--
3
ms
Note: The DM9010B needs the time about 3ms to down load the setting from EEPROM after PWRST# deasserted,
During the period, the processor command (IOR#, IOW#, AEN#) pins are not recognized even no EEPROM present. So,
please note that processor only access DM9010B after PWRST# deasserted 3ms.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com