PCF8533USLASH2DASLASH2 datasheet(31/45 Pages) NXP

31 / 45 page

PCF8533_4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 04 — 5 March 2010

31 of 45

NXP Semiconductors

PCF8533

Universal LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

Large display configurations of up to sixteen PCF8533s can be recognized on the same

I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I2C-bus slave address (SA0).

Cascaded PCF8533s are synchronized. They can share the backplane signals from one

of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCF8533s of the cascade contribute

additional segment outputs but their backplane outputs are left open-circuit (see

Figure 22).

Table 18.

Addressing cascaded PCF8533

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

100

000

011

102

113

004

015

106

117

210

008

019

1010

1111

0012

0113

1014

1115

PCF8533U/2DA/2 Datasheet(PDF) 31 Page - NXP Semiconductors

PCF8533U/2DA/2 Datasheet(HTML) 31 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL