SE97B datasheet(33/53 Pages) NXP

33 / 53 page

SE97B_1

Product data sheet

Rev. 01 — 27 January 2010

33 of 53

NXP Semiconductors

SE97B

DDR memory module temp sensor with integrated SPD

8.9 SMBUS — SMBus register (22h, 8-bit read/write)

Table 26.

SMBUS - SMBus Time-out register bit allocation

Bit

Symbol

RFU

Default

0000000

Access

RRRRR

Bit

Symbol

Disable

Timeout

RFU

Enable

SDTO

Event

Sleep

State

IntrClear

Mode

Flag

Update

Mode

RFU

Disable

ARA

Default

0110001

Access

R/W

Table 27.

SMBus Time-out register bit description

Bit

Symbol

Description

15:8

RFU

reserved; always ‘0’

DisableTimeout Disable SMBus time-out.

0 — SMBus time-out is enabled (default)

1 — SMBus time-out is disabled

When either of the Critical Trip or Alarm Window lock bits is set, this bit

cannot be altered until unlocked.

RFU

reserved; always ‘0’

EnableSDTO

SMBus time-out during Shutdown (CONFIG[8]).

0 — disable SMBus time-out

1 — enable SMBus time-out (default)

Remark: DisableTimeout bit must be a logic 0 to enable this feature.

When either Critical Trip or Alarm Window lock bits are set, this bit

cannot be altered until unlocked.

EventSleep

State[1]

State of EVENT output when SHMD bit is set.

0 — EVENT pin state is frozen

1 — EVENT pin is de-asserted, state based on Polarity bit (default)

When either Critical Trip or Alarm Window lock bits are set, this bit

cannot be altered until unlocked.

IntrClear

Mode[2]

Interrupt Flop Clearing Mode.

0 — allow clearing interrupt flop while in comparator mode (default)

1 — disable clearing interrupt flow while in comparator mode

When either Critical Trip or Alarm Window lock bits are set, this bit

cannot be altered until unlocked.

FlagUpdate

Mode

Update AAW, BAW and ACT flags after each new temperature

conversion.

0 — update AAW, BAW and ACT flags continuously (default)

1 — update flags with new temperature conversion

When either Critical Trip or Alarm Window lock bits are set, this bit

cannot be altered until unlocked.

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