2002-01-15

Page

1

MDST-0014-07

www.vaishali.com

Vaishali Semiconductor

747 Camden Avenue, Suite C

Campbell

CA 95008

Ph. 408.377.6060

Fax 408.377.6063

Applications

•= PECL clock source

General Description

The Vaishali VT73LVP10 is a general purpose TTL (CMOS) to differential LVPECL translator, with active-LOW

enable. The device operates from a single 3.3V supply. When /EN is LOW or open circuit, the device accepts

an LVTTL or LVCMOS input and provides differential LVPECL outputs referenced to the positive supply rail.

When /EN is HIGH, the Q output is set to the LOW state and QN output is set to the HIGH state.

Features

•= 700ps typical propagation delay

•= Differential LVPECL outputs

•= Flow-through pinout

•= -40

•= 5V - tolerant inputs

•= ESD rating >2000V (Human Body

Model) or >200V (Machine Model)

•= Available as die, 8-pin SOIC or 8 pin

MSOP package

Preliminary

VT73LVP10

TTL to Differential LVPECL Translator

with Enable

Figure 1. Functional Block Diagram & Pin Assignment

/EN

QN

Q

NC

4

3

2

1

6

7

8

TTL/

CMOS

LVPECL

5 GND

NC

D

8 pin SOIC/ MSOP

100kΩ