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VG37648041AT Datasheet(PDF) 71 Page - Vanguard International Semiconductor |
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VG37648041AT Datasheet(HTML) 71 Page - Vanguard International Semiconductor |
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71 / 86 page  Document : 1G5-0157 Rev.1 Page 71 VIS Preliminary VG37648041AT 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM A.C Characteristics: Test Conditions: (Ta=0 to 70°C VDDQ=2.5V , VDD=3.3V , or VDD=2.5V A.C. Parameter Symbol -75 -8 Unit Note Min. Max. Min. Max. tCK Access time from CLK/CLK# tAC -0.1 +0.1 -0.1 +0.1 tCK Clock high time tCH 0.45 0.55 0.45 0.55 tCK Clock low time tCL 0.45 0.55 0.45 0.55 ns Clock cycle time CL=3 tCK3Q 5 15 6 15 ns CL=2.5 tCK2.5 6.2 15 7 15 ns CL=2 tCK2 7.5 15 8 15 ns CL=1.5 tCK15 10 15 10 15 tCK Data-in hold time tDH 0.075 0.075 tCK Data-in setup time tDS 0.075 0.075 tCK 18 Data-out high imedance from CLK/CLK# tHZ -0.1 +0.1 -0.1 +0.1 tCK 18 Data-out low impedance from CLK/CLK# tLZ -0.1 +0.1 -0.1 +0.1 tCK DQS-DQ Skew tDSDQ -0.075 +0.075 -0.075 +0.075 tCK DQ/DQS output valid time tDV 0.35 0.35 tCK Write command to first DQS latching transition tDSS 0.75 1.25 0.75 1.25 tCK DQ/DQS input valid time tDSLH 0.40 0.60 0.40 0.60 tCK LOAD MODE REGISTER COMMAND cycle time tMRD 2 2 tCK 22 Write preamble setup time tWPR 0 0 ns 19 Write postamble tWPO 0.4 0.6 0.4 0.6 tCK 20 Write command to DQS Low-Z tWCP 0 0 ns Input hold time tIH 0.15 0.15 tCK Input setup time tIS 0.15 0.15 tCK Read preamble tRPR 0.9 1.1 0.9 1.1 tCK Read postamble tRPO 0.4 0.6 0.4 0.6 tCK ACTIVE to PRECHARGE command tRAS 45 120,000 48 120,000 ns AUTO REFRESH, ACTIVE command period tRC 65 70 ns ACTIVE to READ or WRITE delay tRCD 20 20 ns Refresh period (8192 rows) tREF 64 64 ms PRECHARGE command period tRP 20 20 ns ACTIVE bank A to Active bank B command tRRD 15 20 ns Transition time tT ns Write recovery time tWR 2 2 tCK Write data In to Read Command Delay tWTR 1 1 tCK Exit SELF REFRESH to ACTIVE command tXSR 60 70 ns 21 0.2V ± 0.3V ± 0.2V ± |
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