R5F2L357CDFP datasheet(55/76 Pages) RENESAS

55 / 76 page

REJ03B0293-0020 Rev.0.20

Mar 12, 2010

Page 53 of 72

Under development

Preliminary specification

Specifications in this manual are tentative and subject to change.

R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group

5. Electrical Characteristics

Notes:

Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.

Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2

Note:

To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.

Figure 5.3

Power-on Reset Circuit Characteristics

Table 5.10

Voltage Detection 2 Circuit Characteristics

(VCC = 1.8 to 5.5 V and Topr =

−20 to 85°C (N version) / −40 to 85°C (D version), unless

otherwise specified.)

Symbol

Parameter

Condition

Standard

Unit

Min.

Typ.

Max.

Vdet2

Voltage detection level Vdet2_0

At the falling of VCC

3.70

4.00

4.30

—

Hysteresis width at the rising of Vcc in voltage detection

2 circuit

—0.10—

—

Voltage detection 2 circuit response time (1)

At the falling of Vcc from

5 V to (Vdet2_0

− 0.1) V

—

150

µs

—

Voltage detection circuit self power consumption

VCA27 = 1, VCC = 5.0 V

—

1.7

—

µA

td(E-A)

Waiting time until voltage detection circuit operation

starts (2)

—

100

µs

Table 5.11

Power-on Reset Circuit Characteristics (1)

(Topr =

−20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Symbol

Parameter

Condition

Standard

Unit

Min.

Typ.

Max.

trth

External power VCC rise gradient

—

50000

mV/msec

Notes:

1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection

Circuit of Hardware Manual (REJ09B0585) for details.

2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable

a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain

tw(por) for 1 ms or more.

Vdet0 (1)

0.5 V

Internal

reset signal

tw(por) (2)

Voltage detection 0

circuit response time

Vdet0 (1)

fOCO-S

× 32

fOCO-S

× 32

External

Power VCC

trth

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