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Heat loss

Thermal design must be conducted with the operation under the conditions listed below (which are the guaranteed

temperature range requiring consideration on appropriate margins etc.):

1. Ambient temperature Ta: 100°C or lower

2. Chip junction temperature Tj: 150°C or lower

The chip junction temperature Tj can be considered as follows. See Page 9/9 for θja.

Most of heat loss in BD3537F occurs at the output N-channel FET. The power lost is determined by multiplying the voltage

between VIN and Vo by the output current. As this IC employs the power PKG, the thermal derating characteristics

significantly depends on the pc board conditions. When designing, care must be taken to the size of a pc board to be used.

If VTT_IN = 1.8volts, REF=0.9volts, and Io (Ave)=0.5 A, for instance, the power dissipation is determined as follows:

Power dissipation (W) = {1.8 (V) – 0.9 (V)} × 0.5 (A) = 0.4 (W)

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NOTE FOR USE

1.Absolute maximum ratings

For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working

temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. Because it is

unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute maximum

rating, physical safety measures are requested to be taken, such as fuses, etc.

2.GND potential

Bring the GND terminal potential to the minimum potential in any operating condition.

3.Thermal design

Consider allowable loss (Pd) under actual working condition and carry out thermal design with sufficient margin provided.

4.Terminal-to-terminal short-circuit and erroneous mounting

When the present IC is mounted to a printed circuit board, take utmost care to direction of IC and displacement. In the event

that the IC is mounted erroneously, IC may be destroyed. In the event of short-circuit caused by foreign matter that enters in

a clearance between outputs or output and power-GND, the IC may be destroyed.

5.Operation in strong electromagnetic field

The use of the present IC in the strong electromagnetic field may result in maloperation, to which care must be taken.

6.Built-in thermal shutdown protection circuit

The present IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175°C

(standard value) and has a -15°C (standard value) hysteresis width. When the IC chip temperature rises and the TSD circuit

operates, the output terminal is brought to the OFF state. The built-in thermal shutdown protection circuit (TSD circuit) is first

and foremost intended for interrupt IC from thermal runaway, and is not intended to protect and warrant the IC.

Consequently, never attempt to continuously use the IC after this circuit is activated or to use the circuit with the activation of

the circuit premised.

7.Capacitor across output and GND

In the event a large capacitor is connected across output and GND, when Vcc and VIN are short-circuited with 0V or GND for

some kind of reasons, current charged in the capacitor flows into the output and may destroy the IC. Use a capacitor smaller

than 1000 μF between output and GND.

8.Inspection by set substrate

In the event a capacitor is connected to a pin with low impedance at the time of inspection with a set substrate, there is a fear

of applying stress to the IC. Therefore, be sure to discharge electricity for every process. As electrostatic measures,

provide grounding in the assembly process, and take utmost care in transportation and storage. Furthermore, when the set

substrate is connected to a jig in the inspection process, be sure to turn OFF power supply to connect the jig and be sure to

turn OFF power supply to remove the jig.

9. Inputs to IC terminals

This device is a monolithic IC with P

the N-layer of each element form a PN junction which works as:

・

a diode if the electric potentials at the terminals satisfy the following relationship; GND>Terminal A>Terminal B, or

・

a parasitic transistor if the electric potentials at the terminals satisfy the following relationship; Terminal B>GND Terminal A.

The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,

and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner

that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of

parasitic elements.

Resistor

Transistor (NPN)

N

N

N

P

+

P

+

P

P substrate

GND

Parasitic element

Pin A

N

N

P

+

P

+

P

P substrate

GND

Parasitic element

Pin B

C

B

E

N

GND

Pin A

Parasitic

element

Pin B

Other adjacent elements

E

B

C

GND

Parasitic

element