Production Data

WM8143-12

Wolfson Microelectronics

PD. Rev 4 Nov. 99

7

PIN

NAME

TYPE

DESCRIPTION

28

MCLK

Digital IP

Master clock. This clock is applied at eight, six, three or two times the input pixel rate

depending on the operational mode. MCLK is divided internally to define the ADC

sample rate and to provide the clock source for digital logic

29

DGND

Digital supply

Digital ground (0V)

30

OP[0]

Digital OP

See description for pins 1-10

31

OP[1]

Digital OP

See description for pins 1-10

32

DVDD

Digital supply

Positive digital supply (5V)

Typical Performance

WM8143-12 DNL

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0

512

1024

1536

2048

2560

3072

3584

4096

ADC Code

PGA Gain Code vs Actual Gain

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

2.75

3

3.25

3.5

3.75

4

4.25

4.5

4.75

5

5.25

5.5

5.75

6

6.25

6.5

6.75

7

7.25

7.5

7.75

8

8.25

0

1

2

3

4

5

6

7

8

9

Actual Gain

RED

GREEN

BLUE