Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

FPD33684 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # FPD33684
Description  Low Power, Low EMI, TFT-LCD Column Driver with RSDS??Inputs, 64 Grayshades, and 384 Outputs for XGA/SXGA Applications
PDF  15 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

FPD33684 Datasheet(HTML) 4 Page - National Semiconductor (TI)

  FPD33684 Datasheet HTML 1Page - National Semiconductor (TI) FPD33684 Datasheet HTML 2Page - National Semiconductor (TI) FPD33684 Datasheet HTML 3Page - National Semiconductor (TI) FPD33684 Datasheet HTML 4Page - National Semiconductor (TI) FPD33684 Datasheet HTML 5Page - National Semiconductor (TI) FPD33684 Datasheet HTML 6Page - National Semiconductor (TI) FPD33684 Datasheet HTML 7Page - National Semiconductor (TI) FPD33684 Datasheet HTML 8Page - National Semiconductor (TI) FPD33684 Datasheet HTML 9Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 15 page
background image
AC Electrical Characteristics
Digital AC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PW
CLK
Clock Period
11.7
ns
PW
CLK(L)
Low Clock Pulse Width
5
ns
PW
CLK(H)
High Clock Pulse Width
5
ns
t
setup1
RSDS Data Setup Time
2
ns
t
hold1
RSDS Data Hold Time
0
ns
t
setup2
ENIOx Setup Time
2
ns
t
hold2
ENIOx Hold Time
4
ns
t
PLH1
Start Pulse Fall Delay
C
LINE =15 pF
8
ns
PW
DIO
ENIOx Pulse Width
1
2
T
CLK
PW
CLK1
LOAD Pulse Width
5 T
CLK
5µs
t
LDT
Last Clock to LOAD Delay
5
T
CLK
t
DENSU
LOAD to First ENIO Setup
2
T
CLK
tPOL–CLK1
POL–CLK1 Time
14
ns
Analog AC Characteristics
Supplies: V
SS1 =VSS2 = 0.0V, VDD1 = 3.3V, VDD2 = +9.5V, VHBIAS = 11.0V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
settle 90%
Output Settling Time to 90% of
Final Value
Figure 2 (Note 12)
6µs
t
6-bit accy
Output Settling Time to 6-bit
accuracy
Figure 2 (Note 12)
10
µs
t
RP 90%
Repair Line Output Settling Time
to 90% of Final Value
C
LOAD = 150 pF,
(Note 12)
6µs
t
RP 6-bit accy
Repair Line Output Settling Time
to 6-bit accuracy
C
LOAD = 150 pF,
(Note 12)
10
µs
Note 12: Charge Share Time = 800ns, VGMA1 = 10.3V, VGMA10 = 0.2V, VGMA5 = 5.45V, VGMA6 = 5.05V.
DS200113-11
FIGURE 2. Test Circuit for Output Settling Time Measurements
www.national.com
4



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com