X24012PI datasheet(7/14 Pages) XICOR

7 / 14 page

X24012

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24012

SLAVE

ADDRESS

WORD

ADDRESS n

SLAVE

ADDRESS

DATA n

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24012

SLAVE

ADDRESS

DATA

Current Address Read

Internally the X24012 contains an address counter that

maintains the address of the last word accessed,

incremented by one. Therefore, if the last access (either

a read or write) was to address n, the next read operation

would access data from address n + 1. Upon receipt of

the slave address with R/

W set to one, the X24012

issues an acknowledge and transmits the eight bit word

during the next eight clock cycles. The read operation is

terminated by the master; by not responding with an

acknowledge and by issuing a stop condition. Refer to

Figure 7 for the sequence of address, acknowledge and

data transfer.

Random Read

Random read operations allow the master to access any

memory location in a random manner. Prior to issuing

the slave address with the R/

W bit set to one, the master

must first perform a “dummy” write operation. The mas-

ter issues the start condition, and the slave address

followed by the word address it is to read. After the word

address acknowledge, the master immediately reissues

the start condition and the slave address with the R/

W bit

set to one. This will be followed by an acknowledge from

the X24012 and then by the eight bit word. The read

operation is terminated by the master; by not responding

with an acknowledge and by issuing a stop condition.

Refer to Figure 8 for the address, acknowledge and data

transfer sequence.

Figure 7. Current Address Read

3847 FHD F12

Figure 8. Random Read

3847 FHD F13

X24012PI Datasheet(PDF) 7 Page - Xicor Inc.

X24012PI Datasheet(HTML) 7 Page - Xicor Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Datasheet Download

Link URL