AM1806 datasheet(65/241 Pages) TI

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AM1806

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SPRS658B – FEBRUARY 2010 – REVISED MAY 2010

6.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

6.3

Power Supplies

6.3.1

Power-on Sequence

The device should be powered-on in the following order:

•

1) RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other

supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD

should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.

•

2a) All variable 1.2V - 1.0V core logic supplies (CVDD)

•

2b) All static 1.2V logic supplies (RVDD, VDDA_12_PLL0, VDDA_12_PLL1, USB_CVDD ). If voltage

scaling is not used on the device, groups 2a) and 2b) can be controlled from the same power supply

and powered up together.

•

3) All static 1.8V IO supplies (DVDD18, DDR_DVDD18, USB0_VDDA18 ) and any of the LVCMOS IO

supply groups used at 1.8V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C).

•

4) All analog 3.3V PHY supplies (USB0_VDDA33; this is not required if USB0 is not used) and any of

the LVCMOS IO supply groups used at 3.3V nominal (DVDD3318_A, DVDD3318_B, or

DVDD3318_C).

There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies

operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V

supplies by more than 2 volts.

RESET must be maintained active until all power supplies have reached their nominal values.

6.3.2

Power-off Sequence

The power supplies can be powered-off in any order as long as LVCMOS supplies operated at 3.3V

(DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed static 1.8V supplies by more than 2 volts.

There is no specific required voltage ramp down rate for any of the supplies (except as required to meet

the above mentioned voltage condition).

Peripheral Information and Electrical Specifications

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