PAM1707BZKB4 datasheet(20/198 Pages) TI

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AM1707

SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

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Table 3-7. External Memory Interface B (EMIFB) Terminal Functions (continued)

PIN No.

SIGNAL NAME

TYPE(1)

PULL(2)

MUXED

DESCRIPTION

ZKB

EMB_A[4]/GP7[6]

D11

IPD

EMB_A[3]/GP7[5]

A10

IPD

EMIFB SDRAM row/column

EMB_A[2]/GP7[4]

B10

IPD

address.

EMB_A[1]/GP7[3]

C10

IPD

GPIO

EMB_A[0]/GP7[2]

D10

IPD

EMB_BA[1]/GP7[0]

IPU

EMIFB SDRAM bank address.

EMB_BA[0]/GP7[1]

IPU

EMB_CLK

C14

IPU

EMIF SDRAM clock.

EMB_SDCKE

C13

I/O

IPU

EMIFB SDRAM clock enable.

EMB_WE

K15

IPU

EMIFB write enable

EMIFB SDRAM row address

EMB_RAS

IPU

strobe.

EMB_CAS

L13

IPU

EMIFB column address strobe.

EMB_CS[0]

IPU

EMIFB SDRAM chip select 0.

EMB_WE_DQM[3]

A12

IPU

EMB_WE_DQM[2]

B13

IPU

EMIFB write enable/data mask

for EMB_D.

EMB_WE_DQM[1] /GP5[14]

C15

IPU

GPIO

EMB_WE_DQM[0] /GP5[15]

K14

IPU

3.6.6

Serial Peripheral Interface Modules (SPI0, SPI1)

Table 3-8. Serial Peripheral Interface (SPI) Terminal Functions

No.

SIGNAL NAME

TYPE(1)

PULL(2)

MUXED

DESCRIPTION

ZKB

SPI0

UART0, EQEP0B,

SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4]

I/O

IPU

SPI0 chip select.

GPIO, BOOT

UART0, EQEP0A,

SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3]

I/O

IPU

SPI0 enable.

GPIO, BOOT

SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]

I/O

IPD

eQEP1, GPIO, BOOT

SPI0 clock.

SPI0 data

SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]

I/O

IPD

slave-in-master-out.

eQEP0, GPIO, BOOT

SPI0 data

SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]

I/O

IPD

slave-out-master-in.

SPI1

SPI1_SCS[0] /UART2_TXD/GP5[13]

I/O

IPU

SPI1 chip select.

UART2, GPIO

SPI1_ENA /UART2_RXD/GP5[12]

I/O

IPU

SPI1 enable.

SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]

I/O

IPD

eQEP1, GPIO, BOOT

SPI1 clock.

SPI1 data

SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]

I/O

IPU

slave-in-master-out.

I2C1, GPIO, BOOT

SPI1 data

SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]

I/O

IPU

slave-out-master-in.

(1)

I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2)

IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

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