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TMS320DM365ZCE21 Datasheet(PDF) 55 Page - Texas Instruments |
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TMS320DM365ZCE21 Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 211 page  TMS320DM365 www.ti.com SPRS457C – MARCH 2009 – REVISED APRIL 2010 3.3 Device Clocking 3.3.1 Overview The device requires one primary reference clock. The reference clock frequency may be generated either by crystal input or by external oscillator. The reference clock is the clock at the pins named MXI1/MXO1, and which drives two separate PLL controllers (PLLC1 and PLLC2). PLLC1 generates the clocks required by the ARM, EDMA, VPSS and the rest of the peripherals. PLL2 generates the clock required by the DDR PHY interface and is also capable of providing clocks to the ARM, USB, Video, or Voice Codec modules as well as a flexible clocking option. Figure 3-2 represents the clocking architecture for the ARM subsystem. For more information on device clocking and the system PLL controller please see the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5). Copyright © 2009–2010, Texas Instruments Incorporated Device Configurations 55 Submit Documentation Feedback Product Folder Link(s): TMS320DM365 |
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