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74LVC169 Datasheet(PDF) 10 Page - NXP Semiconductors |
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74LVC169 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 22 page ![]() 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 10 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max tpd propagation delay CP to Qn; see Figure 8 [2] VCC = 1.2 V - 17 - - - ns VCC = 2.7 V 1.5 - 7.2 1.5 9.0 ns VCC = 3.0 V to 3.6 V 1.5 4.0 6.6 1.5 8.5 ns CP to TC; see Figure 8 [2] VCC = 1.2 V - 21 - - - ns VCC = 2.7 V 1.5 - 8.8 1.5 11.0 ns VCC = 3.0 V to 3.6 V 1.5 4.8 7.5 1.5 9.5 ns CET to TC; see Figure 9 [2] VCC = 1.2 V - 19 - - - ns VCC = 2.7 V 1.5 - 7.2 1.5 9.0 ns VCC = 3.0 V to 3.6 V 1.5 4.1 6.2 1.5 8.0 ns U/D to TC; see Figure 10 [2] VCC = 1.2 V - 21 - - - ns VCC = 2.7 V 1.5 - 8.2 1.5 10.5 ns VCC = 3.0 V to 3.6 V 1.5 3.7 6.9 1.5 9.0 ns tW pulse width CP HIGH or LOW; see Figure 8 VCC = 2.7 V 5.0 - - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns tsu set-up time Dn to CP; see Figure 11 VCC = 2.7 V 3.0 - - 3.0 - ns VCC = 3.0 V to 3.6 V 2.5 1.0 - 2.5 - ns PE to CP; see Figure 11 VCC = 2.7 V 3.5 - - 3.5 - ns VCC = 3.0 V to 3.6 V 3.0 1.2 - 3.0 - ns U/D to CP; see Figure 12 VCC = 2.7 V 6.5 - - 6.5 - ns VCC = 3.0 V to 3.6 V 5.5 2.8 - 5.5 - ns CEP, CET to CP; see Figure 12 VCC = 2.7 V 5.5 - - 5.5 - ns VCC = 3.0 V to 3.6 V 4.5 2.1 - 4.5 - ns th hold time Dn, PE, CEP, CET, U/D to CP; see Figure 11 and 12 VCC = 2.7 V 0.0 - - 0.0 - ns VCC = 3.0 V to 3.6 V 0.5 0.0 - 0.5 - ns |
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