PIC18F86K22 datasheet(56/548 Pages) MICROCHIP

56 / 548 page

PIC18F87K22 FAMILY

DS39960B-page 56

Preliminary

 2010 Microchip Technology Inc.

4.1.3

CLOCK TRANSITIONS AND STATUS

INDICATORS

The length of the transition between clock sources is

the sum of two cycles of the old clock source and three

to four cycles of the new clock source. This formula

assumes that the new clock source is stable. The HF-

INTOSC and MF-INTOSC are termed as INTOSC in

this chapter.

Three bits indicate the current clock source and its

status, as shown in Table 4-2. The three bits are:

• OSTS (OSCCON<3>)

• HFIOFS (OSCCON<2>)

• SOSCRUN (OSCCON2<6>)

When the OSTS bit is set, the primary clock is providing

the device clock. When the HFIOFS or MFIOFS bit is

set, the INTOSC output is providing a stable 16 MHz

clock source to a divider that actually drives the device

clock. When the SOSCRUN bit is set, the SOSC oscil-

lator is providing the clock. If none of these bits are set,

either the LF-INTOSC clock source is clocking the

device or the INTOSC source is not yet stable.

If the internal oscillator block is configured as the

primary clock source by the FOSC<3:0> Configuration

bits (CONFIG1H<3:0>), then the OSTS and HFIOFS or

MFIOFS bits can be set when in PRI_RUN or

PRI_IDLE modes. This indicates that the primary clock

(INTOSC output) is generating a stable 16 MHz output.

Entering another INTOSC power-managed mode at

the same frequency would clear the OSTS bit.

4.1.4

MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the

SLEEP

instruction is determined by the setting of the

IDLEN bit at the time the instruction is executed. If

another SLEEP instruction is executed, the device will

enter the power-managed mode specified by IDLEN at

that time. If IDLEN has changed, the device will enter

the new power-managed mode specified by the new

setting.

4.2

Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

4.2.1

PRI_RUN MODE

The PRI_RUN mode is the normal, full-power execu-

tion mode of the microcontroller. This is also the default

mode upon a device Reset, unless Two-Speed Start-up

is enabled. (For details, see Section 28.4 “Two-Speed

Start-up”.) In this mode, the OSTS bit is set. The

HFIOFS or MFIOFS bit may be set if the internal

oscillator block is the primary clock source. (See

Section 3.2 “Control Registers”.)

4.2.2

SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the

“clock-switching” feature offered in other PIC18

devices. In this mode, the CPU and peripherals are

clocked from the SOSC oscillator. This enables lower

power consumption while retaining a high-accuracy

clock source.

SEC_RUN mode is entered by setting the SCS<1:0>

bits to ‘01’. The device clock source is switched to the

SOSC oscillator (see Figure 4-1), the primary oscillator

is shut down, the SOSCRUN bit (OSCCON2<6>) is set

and the OSTS bit is cleared.

On transitions from SEC_RUN mode to PRI_RUN

mode, the peripherals and CPU continue to be clocked

from the SOSC oscillator while the primary clock is

started. When the primary clock becomes ready, a

clock switch back to the primary clock occurs (see

Figure 4-2). When the clock switch is complete, the

SOSCRUN bit is cleared, the OSTS bit is set and the

primary clock is providing the clock. The IDLEN and

SCS bits are not affected by the wake-up and the

SOSC oscillator continues to run.

TABLE 4-2:

SYSTEM CLOCK INDICATOR

Main Clock Source OSTS

HFIOFS or

MFIOFS

SOSCRUN

Primary oscillator

INTOSC (HF-INTOSC

or MF-INTOSC)

Secondary Oscillator

MF-INTOSC or

HF-INTOSC as primary

clock source

LF-INTOSC is running

or INTOSC is not yet

stable

Note 1: Caution should be used when modifying a

single IRCF bit. At a lower VDD, it is

possible to select a higher clock speed

than is supportable by that VDD. Improper

device operation may result if the VDD/

FOSC specifications are violated.

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep

mode. It acts as the trigger to place the

controller into either the Sleep mode or

one of the Idle modes, depending on the

setting of the IDLEN bit.

Note:

The SOSC oscillator can be enabled by

setting the SOSCGO bit (OSCCON2<3>).

If this bit is set, the clock switch to the

SEC_RUN mode can switch immediately

once SCS<1:0> are set to ‘01’.

PIC18F86K22 Datasheet(PDF) 56 Page - Microchip Technology

PIC18F86K22 Datasheet(HTML) 56 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL