CS8415A-CSZ datasheet(15/46 Pages) CIRRUS

15 / 46 page

DS470F4

CS8415A

5. AES3 RECEIVER

The CS8415A includes an AES3 digital audio receiver. A comprehensive buffering scheme provides read access

to the channel status and user data. This buffering scheme is described in Appendix B.

The AES3 receiver accepts and decodes audio and digital data according to the AES3, IEC60958 (S/PDIF), and

EIAJ CP-1201 interface standards. The receiver consists of a differential input stage, driven through pins RXP0

and RXN0, a PLL-based clock recovery circuit, and a decoder which separates the audio data from the channel

status and user data.

External components are used to terminate and isolate the incoming data cables from the CS8415A. These com-

ponents are detailed in Appendix A.

5.1

7:1 S/PDIF Input Multiplexer

The CS8415A employs a 7:1 S/PDIF Input Multiplexer to accommodate up to seven channels of input digital

audio data. Digital audio data is single-ended and input through the RXP[0:6] pins. When any portion of the

multiplexer is implemented, unused RXP pins should be tied to ground, and RXN0 must be AC-coupled to

ground. The multiplexer select line control is accessed through bits MUX[2:0] in the Control 2 register. The

multiplexer defaults to RXP0. Therefore, the default configuration is for a differential signal to be input

through RXP0 & RXN0. Please see Appendix A for recommended input circuits.

5.2

OMCK System Clock Mode

A special clock switching mode is available that allows the clock that is input through the OMCK pin to be

output through the RMCK pin. This feature is controlled by the SWCLK bit in register 1 of the control regis-

ters. When the PLL loses lock, the frequency of the VCO drops to 300 kHz. The clock switching mode allows

the clock input through OMCK to be used as a clock in the system without any disruption when the PLL loses

lock. For example, when the input is removed from the receiver. When SWCLK is enabled and this mode is

implemented, RMCK is an output and is not bi-directional. This clock switching is performed glitch-free.

Please note that internal circuitry associated with RMCK is not driven by OMCK. This means that OSCLK

and OLRCK continue to be derived from the PLL and are not usable in this mode. This function is available

only in software mode.

5.3

PLL, Jitter Attenuation, and Varispeed

Please see Appendix C for general description of the PLL, selection of recommended PLL filter compo-

nents, and layout considerations. Figure 5 shows the recommended configuration of the two capacitors and

one resistor that comprise the PLL filter.

5.4

Error Reporting and Hold Function

While decoding the incoming AES3 data stream, the CS8415A can identify several kinds of error, indicated

in the Receiver Error register. The UNLOCK bit indicates whether the PLL is locked to the incoming AES3

data. The V bit reflects the current validity bit status. The CONF (confidence) bit is the logical OR of BIP and

UNLOCK. The BIP (bi-phase) error bit indicates an error in incoming bi-phase coding. The PAR (parity) bit

indicates a received parity error.

The error bits are "sticky" - they are set on the first occurrence of the associated error and will remain set

until the user reads the register through the control port. This enables the register to log all unmasked errors

that occurred since the last time the register was read.

The Receiver Error Mask register allows masking of individual errors. The bits in this register serve as

masks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error is un-

masked, which implies the following: its occurrence will be reported in the receiver error register, induce a

CS8415A-CSZ Datasheet(PDF) 15 Page - Cirrus Logic

CS8415A-CSZ Datasheet(HTML) 15 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL