PCA9530_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 26 February 2009

3 of 24

NXP Semiconductors

PCA9530

5.

Pinning information

5.1 Pinning

5.2 Pin description

6.

Functional description

Refer to Figure 1 “Block diagram”.

6.1 Device addressing

Following a START condition, the bus master must output the address of the slave it is

accessing. The address of the PCA9530 is shown in Figure 4. To conserve power, no

internal pull-up resistor is incorporated on the hardware selectable address pin and it must

be pulled HIGH or LOW.

Fig 2.

Pin configuration for SO8

Fig 3.

Pin configuration for TSSOP8

(MSOP8)

PCA9530D

A0

LED0

SDA

LED1

SCL

RESET

002aae496

1

2

3

4

6

5

8

7

PCA9530DP

A0

LED0

SDA

LED1

SCL

002aae497

1

2

3

4

6

5

8

7

RESET

Table 2.

Pin description

Symbol

Pin

Description

A0

1

address input 0

LED0

2

LED driver 0

LED1

3

LED driver 1

4

supply ground

RESET

5

active LOW reset input

SCL

6

serial clock line

SDA

7

serial data line

8

supply voltage

Fig 4.

Slave address

002aae499

1

1

0

0

0

0

A0 R/W

fixed

slave address

hardware

selectable