PCA9533_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 27 April 2009

4 of 24

NXP Semiconductors

PCA9533

6.

Functional description

Refer to Figure 1 “Block diagram of PCA9533”.

6.1 Device address

Following a START condition, the bus master must output the address of the slave it is

accessing. The address of the PCA9533/01 is shown in Figure 4 and the address of

PCA9533/02 is shown in Figure 5.

The last bit of the address byte defines the operation to be performed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9533, which will be stored in the Control register.

The lowest 3 bits are used as a pointer to determine which register will be accessed.

If the Auto-Increment (AI) flag is set, the three low order bits of the Control register are

automatically incremented after a read or write. This allows the user to program the

registers sequentially. The contents of these bits will rollover to ‘000’ after the last register

is accessed.

When Auto-Increment flag is set (AI = 1) and a read sequence is initiated, the sequence

must start by reading a register different from the INPUT register (B2 B1 B0

≠ 0 0 0).

Only the 3 least significant bits are affected by the AI flag. Unused bits must be

programmed with zeroes.

SCL

6

serial clock line

SDA

7

serial data line

8

supply voltage

Table 3.

Symbol

Pin

Description

Fig 4.

PCA9533/01 slave address

Fig 5.

PCA9533/02 slave address

002aae627

1

1

0

0

0

1

0

R/W

slave address

002aae628

1

1

0

0

0

1

1

R/W

slave address

Reset state: 00h

Fig 6.

Control register

B0

002aad744

0

0

0

AI

0

B2

B1

register address

Auto-Increment

flag