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PCA9539D Datasheet(PDF) 21 Page - NXP Semiconductors |
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PCA9539D Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 31 page ![]() PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 21 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Fig 22. Expanded view of read input port register Fig 23. Expanded view of write to output port register Rise and fall times refer to VIL and VIH. Fig 24. I2C-bus timing diagram SCL 002aad734 21 0 A P 70 % 30 % SDA input 50 % INT tv(INT_N) trst(INT_N) th(Q) tsu(D) SCL 002aad735 21 0 A P 70 % SDA output 50 % tv(Q) SCL SDA tHD;STA tSU;DAT tHD;DAT tf tBUF tSU;STA tLOW tHIGH tVD;ACK 002aab285 tSU;STO protocol START condition (S) bit 7 MSB (A7) bit 6 (A6) bit 1 (D1) bit 0 (D0) 1 / fSCL tr tVD;DAT acknowledge (A) STOP condition (P) |
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