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PCF85133U/2DA/1 Datasheet(PDF) 27 Page - NXP Semiconductors

Part # PCF85133U/2DA/1
Description  Universal LCD driver for low multiplex rates
PDF  41 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF85133U/2DA/1 Datasheet(HTML) 27 Page - NXP Semiconductors

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PCF85133_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 17 February 2009
27 of 41
NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
11. Dynamic characteristics
[1]
Typical output duty cycle of 50 %.
[2]
The corresponding frame frequency is
.
[3]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
[4]
For I2C-bus timings see Figure 19.
Table 17.
Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock
Internal: output pin CLK
fclk
clock frequency
FF = VDD
[1][2]
1440
1970
2640
Hz
FF = VSS
[1][2]
1920
2640
3600
Hz
ffr
frame frequency
FF = VDD
60
82
110
Hz
FF = VSS
80
110
150
Hz
External: input pin CLK
fclk(ext)
external clock frequency
[2]
800
-
3600
Hz
tclk(H)
HIGH-level clock time
130
-
-
µs
tclk(L)
LOW-level clock time
130
-
-
µs
Synchronization: input pin SYNC
tPD(SYNC_N)
SYNC propagation delay
-
30
-
ns
tSYNC_NL
SYNC LOW time
1
-
-
µs
Outputs: pins BP0 to BP3 and S0 to S79
tPD(drv)
driver propagation delay
VLCD = 5 V
-
-
30
µs
I2C-bus: timing[3][4]
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tHIGH
HIGH period of the SCL clock
0.6
-
-
µs
tLOW
LOW period of the SCL clock
1.3
-
-
µs
Pin SDA
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pins SCL and SDA
tBUF
bus free time between a STOP and START condition
1.3
-
-
µs
tSU;STO
set-up time for STOP condition
0.6
-
-
µs
tHD;STA
hold time (repeated) START condition
0.6
-
-
µs
tSU;STA
set-up time for a repeated START condition
0.6
-
-
µs
tr
rise time of both SDA and SCL signals
-
-
0.3
µs
tf
fall time of both SDA and SCL signals
-
-
0.3
µs
Cb
capacitive load for each bus line
-
-
400
pF
tw(spike)
spike pulse width
on bus
-
-
50
ns
f
fr
f
clk
24
---------
=



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