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PRTR5V0U4Y Datasheet(PDF) 3 Page - NXP Semiconductors |
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PRTR5V0U4Y Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 10 page ![]() PRTR5V0U4Y_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 8 May 2008 3 of 10 NXP Semiconductors PRTR5V0U4Y Integrated quad ultra-low capacitance ESD protection 6. Characteristics 7. Application information 7.1 IEEE 1394a/b protection The PRTR5V0U4Y is optimized to protect both the IEEE 1394 physical layer and the IEEE 1394 connector ports against ESD. Table 5. Characteristics Tamb =25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit C(I/O-GND) input/output to ground capacitance pins 1, 3, 4 and 6; VI = 0 V; f = 1 MHz; VCC = 3.0 V - 1.0 - pF ILR reverse leakage current pins 1, 3, 4 and 6 to ground; VI = 3.0 V - - 100 nA VBR breakdown voltage Zener diode; I = 1 mA 6 - 9 V VF forward voltage - 0.7 - V Fig 1. Typical application for IEEE 1394a/b ESD protection 001aag050 1 M Ω 56 Ω 56 Ω 56 Ω 56 Ω 5 k Ω 1 nF 10 nF 220 pF 1 µF 1 2 3 TPB+ TPB − TPA+ IEEE 1394 PHYSICAL LAYER TPA − 6 5 4 BUS PWR TPB+ GND Shld2 TPB − TPA+ TPA − PWR Shld1 4 2 8 3 6 5 1394 CONNECTOR 1 7 TPBIAS |
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