SC16C751B datasheet(15/32 Pages) NXP

15 / 32 page

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

15 of 32

NXP Semiconductors

SC16C751B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.4 Interrupt Status Register (ISR)

The SC16C751B provides four levels of prioritized interrupts to minimize external software

interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status

bits. Performing a read cycle on the ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are acknowledged until the pending

interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is

cleared. However, it should be noted that only the current pending interrupt is cleared by

the read. A lower level interrupt may be seen after re-reading the interrupt status bits.

Table 10 “Interrupt source” shows the data values (bit 0 to bit 4) for the four prioritized

interrupt levels and the interrupt sources associated with each of these interrupt levels.

Table 10.

Interrupt source

Priority

level

ISR[3]

ISR[2]

ISR[1]

ISR[0]

Source of the interrupt

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding Register Empty)

MSR (Modem Status Register)

Table 11.

Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is not

being used. They are set to a logic 1 when the FIFOs are enabled.

logic 0 or cleared = default condition

ISR[5]

64-byte FIFO enable.

logic 0 = 16-byte operation

logic 1 = 64-byte operation

ISR[4]

not used

3:1

ISR[3:1]

INT priority bit 2 to bit 0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 10).

logic 0 or cleared = default condition

ISR[0]

INT status.

logic 0 = an interrupt is pending and the ISR contents may be used

as a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

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