MC68HC11F1CPU3 datasheet(73/158 Pages) FREESCALE

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RESETS AND INTERRUPTS

TECHNICAL DATA

5-11

The illegal opcode trap mechanism works for all unimplemented opcodes on all four

opcode map pages. The address stacked as the return address for the illegal opcode

interrupt is the address of the first byte of the illegal opcode. Otherwise, it would be

almost impossible to determine whether the illegal opcode had been one or two bytes.

The stacked return address can be used as a pointer to the illegal opcode so the illegal

opcode service routine can evaluate the offending opcode.

5.4.4 Software Interrupt

SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhib-

ited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit,

once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, or

until user software clears the I bit in the CCR.

5.4.5 Maskable Interrupts

The maskable interrupt structure of the MCU can be extended to include additional ex-

ternal interrupt sources through the IRQ pin. The default configuration of this pin is a

low-level sensitive wired-OR network. When an event triggers an interrupt, a software

accessible interrupt flag is set. When enabled, this flag causes a constant request for

interrupt service. After the flag is cleared, the service request is released.

5.4.6 Reset and Interrupt Processing

Figure 5-1 and Figure 5-3 illustrate the reset and interrupt process. Figure 5-1 illus-

trates how the CPU begins from a reset and how interrupt detection relates to normal

opcode fetches. Figure 5-3 is an expansion of a block in Figure 5-1 and illustrates in-

terrupt priorities. Figure 5-5 shows the resolution of interrupt sources within the SCI

subsystem.

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MC68HC11F1CPU3 Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc