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HT46R01M Datasheet(PDF) 45 Page - Holtek Semiconductor Inc |
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HT46R01M Datasheet(HTML) 45 Page - Holtek Semiconductor Inc |
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45 / 69 page ![]() HT46R01M/HT46R02M/HT48R01M/HT48R02M Rev. 1.10 45 March 8, 2010 Programming Considerations When programming, special attention must be given to the PCR[3:0] bits in the register. If these bits are all cleared to zero no external pins will be selected for use as A/D input pins allowing the pins to be used as normal I/O pins. When this happens the internal A/D circuitry will be power down. Setting the ADONB bit high has the ability to power down the internal A/D circuitry, which may be an important consideration in power sensitive applications. A/D Transfer Function As the device contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD voltage, this gives a single bit analog input value of VDD/4096. The diagram show the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Note that to reduce the quantisation error, a 0.5 LSB off- set is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD level. A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. t A D C A / D c o n v e r s i o n t i m e 0 0 0 B x x B x x x B - P C R [ 3 : 0 ] i s n o t e q u a l t o " 0 " 1 0 B S T A R T E O C B P C R 3 ~ P C R 0 A C S 1 ~ A C S 0 P o w e r - o n R e s e t E n d o f A / D c o n v e r s i o n 1 : D e f i n e p o r t c o n f i g u r a t i o n 2 : S e l e c t a n a l o g c h a n n e l A / D c l o c k m u s t b e f s y s , f S Y S / 2 , f S Y S / 4 , f S Y S / 8 , f S Y S / 1 6 o r f S Y S / 3 2 t A D C S = 4 t A D t A D C = 1 6 t A D N o t e : S t a r t o f A / D c o n v e r s i o n R e s e t A / D c o n v e r t e r A / D s a m p l i n g t i m e t A D C S 0 0 B S t a r t o f A / D c o n v e r s i o n R e s e t A / D c o n v e r t e r 0 1 B S t a r t o f A / D c o n v e r s i o n R e s e t A / D c o n v e r t e r E n d o f A / D c o n v e r s i o n A / D s a m p l i n g t i m e t A D C S A D C m o d u l e O N A D O N B o f f o n o n t O N 2 S T t A D C A / D c o n v e r s i o n t i m e A/D Conversion Timing F F E H ( ) A / D C o n v e r s i o n R e s u l t F F F H F F D H 0 3 H 0 2 H 0 1 H 0 . 5 L S B 0 1 2 3 4 0 9 3 4 0 9 4 4 0 9 5 4 0 9 6 A n a l o g I n p u t V o l t a g e 1 . 5 L S B V D D 4 0 9 6 Ideal A/D Transfer Function |
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