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SSM3K7002BFU Datasheet(PDF) 2 Page - Toshiba Semiconductor

Part # SSM3K7002BFU
Description  High-Speed Switching Applications Analog Switch Applications
PDF  5 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

SSM3K7002BFU Datasheet(HTML) 2 Page - Toshiba Semiconductor

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SSM3K7002BFU
2009-11-26
2
Electrical Characteristics (Ta = 25°C)
Characteristics
Symbol
Test Condition
Min
Typ
Max
Unit
Gate leakage current
IGSS
VGS = ± 20 V, VDS = 0 V
⎯
⎯
± 10
μA
V (BR) DSS
ID = 10 mA, VGS = 0 V
60
⎯
⎯
Drain-source breakdown voltage
V (BR) DSX
ID = 10 mA, VGS = -10 V
45
⎯
⎯
V
Drain cutoff current
IDSS
VDS = 60 V, VGS = 0 V
⎯
⎯
1
μA
Gate threshold voltage
Vth
VDS = 10 V, ID = 0.25 mA
1.5
⎯
3.1
V
Forward transfer admittance
⎪Yfs⎪
VDS = 10 V, ID = 200 mA
(Note 2)
225
⎯
⎯
mS
ID = 500 mA, VGS = 10 V
(Note 2)
⎯
1.62
2.1
ID = 100 mA, VGS = 5 V
(Note 2)
⎯
1.90
2.6
Drain-source ON-resistance
RDS (ON)
ID = 100 mA, VGS = 4.5 V
(Note 2)
⎯
2.10
3.3
Ω
Input capacitance
Ciss
⎯
17.0
⎯
Reverse transfer capacitance
Crss
⎯
1.9
⎯
Output capacitance
Coss
VDS = 25 V, VGS = 0 V, f = 1 MHz
⎯
3.6
⎯
pF
Turn-on delay time
td(on)
⎯
3.3
6.6
Switching time
Turn-off delay time
td(off)
VDD = 30 V , ID = 200 mA ,
VGS = 0 to 10 V
⎯
14.5
40
ns
Drain-source forward voltage
VDSF
ID = -200 mA, VGS = 0 V
(Note 2)
⎯
-0.84
-1.2
V
Note2: Pulse test
Switching Time Test Circuit
Precaution
Let Vth be the voltage applied between gate and source that causes the drain current (ID) to be low (0.25 mA for the
SSM3K7002BFU). Then, for normal switching operation, VGS(on) must be higher than Vth, and VGS(off) must be lower
than Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on).
Take this into consideration when using the device
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
(c) VOUT
(b) VIN
(a) Test circuit
td(on)
90 %
10 %
0 V
10 V
10 %
90 %
td(off)
tr
tf
VDD
VDS (ON)
VDD = 30 V
Duty
≤ 1%
VIN: tr, tf < 2 ns
(Zout = 50 Ω)
Common Source
Ta
= 25 °C
10 V
0
10
μs
VDD
OUT
IN
RL



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