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PIC18F14K22-E/ML Datasheet(PDF) 39 Page - Microchip Technology |
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PIC18F14K22-E/ML Datasheet(HTML) 39 Page - Microchip Technology |
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39 / 388 page  2010 Microchip Technology Inc. Preliminary DS41365D-page 39 PIC18F1XK22/LF1XK22 TABLE 3-2: REGISTER FILE SUMMARY (PIC18F1XK22/LF1XK22) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 257, 28 TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 257, 28 TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 257, 28 STKPTR STKOVF STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 257, 29 PCLATU — — — Holding Register for PC<20:16> ---0 0000 257, 28 PCLATH Holding Register for PC<15:8> 0000 0000 257, 28 PCL PC, Low Byte (PC<7:0>) 0000 0000 257, 28 TBLPTRU — — — Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 257, 52 TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 257, 52 TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 257, 52 TABLAT Program Memory Table Latch 0000 0000 257, 52 PRODH Product Register, High Byte xxxx xxxx 257, 63 PRODL Product Register, Low Byte xxxx xxxx 257, 63 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 0000 000x 257, 67 INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP — RABIP 1111 -1-1 257, 68 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 257, 69 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 257, 44 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 257, 44 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 257, 44 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 257, 44 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of FSR0 offset by W N/A 257, 44 FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 257, 44 FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 257, 44 WREG Working Register xxxx xxxx 257 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 257, 44 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 257, 44 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 257, 44 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 257, 44 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of FSR1 offset by W N/A 257, 44 FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 258, 44 FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 258, 44 BSR — — — — Bank Select Register ---- 0000 258, 33 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 258, 44 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 258, 44 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 258, 44 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 258, 44 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by W N/A 258, 44 FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 258, 44 FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 258, 44 STATUS — — —N OV Z DC C ---x xxxx 258, 42 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See Section 21.4 “Brown-out Reset (BOR)”. 2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is read-only. |
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