PIC16F54-ESLASHSOG datasheet(35/88 Pages) MICROCHIP

35 / 88 page

DS41213D-page 33

PIC16F5X

7.0

TIMER0 MODULE AND TMR0

The Timer0 module has the following features:

• 8-bit Timer/Counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 7-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 7-2 and Figure 7-3).

The user can work around this by writing an adjusted

value to the TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

incrementing edge is determined by the source edge

select bit T0SE (OPTION<4>). Clearing the T0SE bit

selects the rising edge. Restrictions on the external

clock input are discussed in detail in Section 7.1

“Using Timer0 with an External Clock”.

The prescaler assignment is controlled in software by

the control bit PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4,...,

1:256 are selectable. Section 7.2 “Prescaler” details

the operation of the prescaler.

A summary of registers associated with the Timer0

module is found in Table 7-1.

FIGURE 7-1:

TIMER0 BLOCK DIAGRAM

FIGURE 7-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER

Note:

The prescaler may be used by either the

Timer0 module or the Watchdog Timer, but

not both.

Note 1:

Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in Section 3.4 “Option Register”.

The prescaler is shared with the Watchdog Timer (Figure 7-5).

T0CKI

T0SE(1)

T0CS(1)

FOSC/4

Programmable

Prescaler(2)

Sync with

Internal

Clocks

TMR0 Reg

PSout

(2 cycle delay)

PSout

Data Bus

PSA(1)

PS2, PS1, PS0(1)

Sync

PC - 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

Timer0

PC + 1

PC + 2

PC + 3

PC + 4

PC + 5

PC + 6

T0 + 1

T0 + 2

NT0

NT0 + 1

NT0 + 2

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0 + 2

Instruction

Executed

PIC16F54-E/SOG Datasheet(PDF) 35 Page - Microchip Technology

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