PIC16F685-ESLASHML datasheet(118/306 Pages) MICROCHIP

118 / 306 page

PIC16F631/677/685/687/689/690

DS41262E-page 116

9.3

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 9-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 9-4.

The maximum recommended impedance for analog

sources is 10 k

Ω. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 9-1 may be used. This equation

assumes that 1/2 LSb error is used (1024 steps for the

ADC). The 1/2 LSb error is the maximum error allowed

for the ADC to meet its specified resolution.

EQUATION 9-1:

ACQUISITION TIME EXAMPLE

TACQ

Amplifier Settling Time

Hold Capacitor Charging Time

Temperature Coefficient

TAMP

TCOFF

2μsTC

Temperature - 25°C

() 0.05μs/°C

()

[]

CHOLD RIC

RSS

() ln(1/2047)

–

10pF 1k

Ω 7kΩ 10kΩ

()

–

ln(0.0004885)

1.37

μs

TACQ

2μS

1.37μS

50°C- 25°C

() 0.05μS/°C

()

[]

4.67μS

VAPPLIED 1e

–

---------

–

⎝⎠

⎜⎟

⎛⎞

VAPPLIED 1

() 1

–

--------------------------

–

⎝⎠

⎛⎞

VAPPLIED 1

() 1

–

--------------------------

–

⎝⎠

⎛⎞

VCHOLD

VAPPLIED 1e

–

----------

–

⎝⎠

⎜⎟

⎛⎞

VCHOLD

;[1] VCHOLD charged to within 1/2 lsb

;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]

The value for TC can be approximated with the following equations:

Solving for TC:

Therefore:

Temperature

50°C and external impedance of 10k

Ω 5.0V VDD

Assumptions:

Note: Where n = number of bits of the ADC.

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