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PIC16F685-E/ML Datasheet(PDF) 119 Page - Microchip Technology |
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PIC16F685-E/ML Datasheet(HTML) 119 Page - Microchip Technology |
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119 / 306 page ![]() © 2008 Microchip Technology Inc. DS41262E-page 117 PIC16F631/677/685/687/689/690 FIGURE 9-4: ANALOG INPUT MODEL FIGURE 9-5: ADC TRANSFER FUNCTION Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k Ω. This is required to meet the pin leakage specification. CPIN VA Rs ANx 5 pF VDD VT = 0.6V VT = 0.6V I LEAKAGE(1) RIC ≤ 1k Sampling Switch SS Rss CHOLD = 10 pF VSS/VREF- 6V Sampling Switch 5V 4V 3V 2V 567 8 9 10 11 (k Ω) VDD Legend: CPIN VT I LEAKAGE RIC SS CHOLD = Input Capacitance = Threshold Voltage = Leakage current at the pin due to = Interconnect Resistance = Sampling Switch = Sample/Hold Capacitance various junctions RSS Note 1: See Section 17.0 “Electrical Specifications”. 3FFh 3FEh 3FDh 3FCh 004h 003h 002h 001h 000h Full-Scale 3FBh 1 LSB ideal VSS/VREF- Zero-Scale Transition VDD/VREF+ Transition 1 LSB ideal Full-Scale Range Analog Input Voltage |
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