ST72324J2 datasheet(159/164 Pages) STMICROELECTRONICS

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15 KNOWN LIMITATIONS

15.1 ALL DEVICES

15.1.1 External RC option

The External RC clock source option described in

previous datasheet revisions is no longer support-

ed and has been removed from this specification.

15.1.2 CSS Function

The Clock Security System function has been re-

moved from the datasheet.

15.1.3 Safe Connection of OSC1/OSC2 Pins

The OSC1 and/or OSC2 pins must not be left un-

connected otherwise the ST7 main oscillator may

start and, in this configuration, could generate an

fOSC clock frequency in excess of the allowed

maximum (>16MHz.), putting the ST7 in an un-

safe/undefined state. Refer to Section 6.2 on page

24.

15.1.4 Unexpected Reset Fetch

If an interrupt request occurs while a “POP CC” in-

struction is executed, the interrupt controller does

not recognise the source of the interrupt and, by

default, passes the RESET vector address to the

CPU.

Workaround

To solve this issue, a “POP CC” instruction must

always be preceded by a “SIM” instruction.

15.1.5

Clearing

active

interrupts

outside

interrupt routine

When an active interrupt request occurs at the

same time as the related flag is being cleared, an

unwanted reset may occur.

Note: clearing the related interrupt mask will not

generate an unwanted reset

Concurrent interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

Perform SIM and RIM operation before and after

resetting an active interrupt request.

Example:

SIM

reset interrupt flag

RIM

Nested interrupt context:

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine with higher or identical priority level

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

PUSH CC

SIM

reset interrupt flag

POP CC

15.1.6 External Interrupt Missed

To avoid any risk of generating a parasitic inter-

rupt, the edge detector is automatically disabled

for one clock cycle during an access to either DDR

and OR. Any input signal edge during this period

will not be detected and will not generate an inter-

rupt.

This case can typically occur if the application re-

freshes the port configuration registers at intervals

during runtime.

Workaround

The workaround is based on software checking

the level on the interrupt pin before and after writ-

ing to the PxOR or PxDDR registers. If there is a

level change (depending on the sensitivity pro-

grammed for this pin) the interrupt routine is in-

voked using the call instruction with three extra

PUSH instructions before executing the interrupt

routine (this is to make the call compatible with the

IRET instruction at the end of the interrupt service

routine).

But detection of the level change does ensure that

edge occurs during the critical 1 cycle duration and

the interrupt has been missed. This may lead to

occurrence of same interrupt twice (one hardware

and another with software call).

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