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68HC805P18 Datasheet(PDF) 97 Page - Freescale Semiconductor, Inc |
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68HC805P18 Datasheet(HTML) 97 Page - Freescale Semiconductor, Inc |
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97 / 111 page ![]() GENERAL RELEASE SPECIFICATION ELECTRICAL SPECIFICATIONS Rev. 1.0 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 13.6 DC Electrical Characteristics (V DD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C) Characteristic Symbol Min Typ Max Unit Output Voltage ILoad = 10.0 µA VOL VOH — VDD –0.1 — — 0.1 — V Output High Voltage (ILoad = –0.8 mA) PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT VOH VDD –0.8 — — V Output Low Voltage (ILoad = 1.6 mA) PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT VOL — — 0.4 V Input High Voltage PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT, TCAP/PD7, IRQ, RESET, OSC1 VIH 0.7 x VDD —VDD V Input Low Voltage PA0–PA7, PB5–PB7, PC0–PC7, PD5, TCAP/PD7, IRQ, RESET, OSC1 VIL VSS — 0.2 x VDD V Supply Current Run Wait (see Note 3) Stop (see Note 8) 25 °C 0 °C to +70 °C (Standard) –40 °C to +85 °C (Extended) –40 °C to +125 °C (Automotive IDD — — — — — — 4.75 2.75 TBD TBD TBD TBD 7.50 5.00 350 400 500 500 mA mA µA µA µA µA I/O Ports Hi-Z Leakage Current PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT, TCAP/PD7 IIL —— ±10 µA I/O Ports Switch Resistance (Pullup Enabled PA0–PA7) RPTA 62 — 102 k A/D Ports Hi-Z Leakage Current PC3–PC7 IIL —— ±1 µA Input Current RESET, IRQ, OSC1 IIN —— ±1 µA Capacitance Ports (as Input or Output) RESET, IRQ COUT CIN — — — — 12 8 pF EEPROM Program/Erase Time (128 Byte Array) Byte Block (Erase Only) Bulk (Erase Only) — — — 2 5 10 10 15 50 ms Low Voltage Reset Voltage 3.6 3.8 — V NOTES: 1. All values shown reflect average measurements. 2. Typical vlaues at midpoint of voltage range, 25 °C only. 3. Wait IDD with active systems: Timer, SIOP, and A/D. 4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2 5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V 6. Stop IDD measured with OSC1 = VSS 7. Wait IDD is affected linearly by the OSC2 capacitance. 8. Stop IDD maximum values given with LVR option enabled. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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