MAC7200 datasheet(159/976 Pages) FREESCALE

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Exception Handling

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

— SRAM access produces an ECC error

— Any SRAM access from $5000 to $7FFF (mirrored on a 32K boundary) — only on MAC72x2.

•

AIPS (See Section 9.9, “Peripheral Bus Memory Map” for a list of PACR/OPACR registers)

— User mode access to any AIPS slave with the corresponding SP bit set in the PACR/OPACR

— Write to any AIPS slave with the corresponding WP bit set in the PACR/OPACR register.

— Any access from an untrusted master to any AIPS slave with the corresponding TP bit set in

the PACR/OPACR register.

— Any access to an AIPS slave that is not implemented (i.e.-marked as “Reserved” in the

documentation)

•

Access to a Peripheral Bus peripheral is aborted by the peripheral itself.

— Access to reserved addresses

— Access to locked registers (See AXBS registers for an example)

— Access to Supervisor only register when in User mode

The list is similar for the DMA, although the reporting mechanism is different (i.e.-no fault information is

available, only an error is reported). However, on the DMA, the contents of the TCD may be examined to

determine the cause of an aborted transfer.

Note that Instructions Aborts are only taken when the instruction enters the execution phase of the ARM7

pipeline.

In addition to flagging aborted instruction fetches, this exception is also used to implement the Non

Maskable Interrupt (NMI). Please refer to Section 7.3.4, “Non-Maskable Interrupt (NMI) for more details.

This means that the Instruction Abort ISR should first check to see if an NMI is pending before attempting

to service an aborted instruction fetch.

7.2.5

Data Abort

Address: $0000 0010

See Section 7.2.4, “Prefetch (Instruction) Abort” for details of special features. The Data Abort exception

is not used for the implementation of the NMI, and behaves as normal.

7.2.6

IRQ

Address: $0000 0018

7.2.7

FIQ

Address: $0000 001C

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