ST7MC2XX datasheet(52/309 Pages) STMICROELECTRONICS

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POWER SAVING MODES (Cont’d)

8.4 ACTIVE-HALT AND HALT MODES

Active-halt and Halt modes are the two lowest

power consumption modes of the MCU. They are

both entered by executing the ‘HALT’ instruction.

The decision to enter either in Active-halt or Halt

mode is given by the MCC/RTC interrupt enable

flag (OIE bit in MCCSR register).

8.4.1 ACTIVE-HALT MODE

Active-halt mode is the lowest power consumption

mode of the MCU with a real-time clock available.

It is entered by executing the ‘HALT’ instruction

when the OIE bit of the Main Clock Controller Sta-

tus register (MCCSR) is set (see section 6.4 on

page 37 for more details on the MCCSR register).

The MCU can exit Active-halt mode on reception

of either an MCC/RTC interrupt, a specific inter-

rupt

(see

Table 8,

“Interrupt

Mapping,”

page 44) or a RESET. When exiting Active-halt

mode by means of an interrupt, no 256 or 4096

CPU cycle delay occurs. The CPU resumes oper-

ation by servicing the interrupt or by fetching the

reset vector which woke it up (see Figure 29).

When entering Active-halt mode, the I[1:0] bits in

the CC register are forced to ‘10b’ to enable inter-

rupts. Therefore, if an interrupt is pending, the

MCU wakes up immediately.

In Active-halt mode, only the main oscillator and its

associated counter (MCC/RTC) are running to

keep a wake-up time base. All other peripherals

are not clocked except those which get their clock

supply from another clock generator (such as ex-

ternal or auxiliary oscillator).

The safeguard against staying locked in Active-

halt mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of

the oscillators is selected (MCCSR.OIE bit set),

entering Active-halt mode while the Watchdog is

active does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

Figure 28. Active-halt Timing Overview

Figure 29. Active-halt Mode Flow-chart

Notes:

1. This delay occurs only if the MCU exits Active-

halt mode by means of a RESET.

2. Peripheral clocked with an external clock source

can still be active.

3. Only the MCC/RTC interrupt and some specific

interrupts can exit the MCU from Active-halt mode

(such as external interrupt). Refer to Table 8, “In-

terrupt Mapping,” on page 44 for more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and restored when the CC

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

Halt mode

Active-halt mode

HALT

RUN

256 OR 4096 CPU

CYCLE DELAY 1)

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[MCCSR.OIE=1]

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY

(MCCSR.OIE=1)

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