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PC312XDP512F0CFVR Datasheet(PDF) 356 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Datasheet(HTML) 356 Page - Freescale Semiconductor, Inc |
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356 / 1348 page  Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.21 356 Freescale Semiconductor Figure 7-70. 16-Bit Pulse Accumulators Block Diagram Figure 7-71. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A Edge Detector P7 P0 Bus Clock Divide by 64 Clock Select CLK0 CLK1 4:1 MUX TIMCLK (Timer Clock) Prescaled Clock (PCLK) Interrupt MUX (PAMOD) Edge Detector PACA Delay Counter Interrupt PACB 8-Bit PAC3 (PACN3) 8-Bit PAC2 (PACN2) 8-Bit PAC1 (PACN1) 8-Bit PAC0 (PACN0) Px Edge Delay 16-Bit Main Timer TCx Input TCxH I.C. BUFEN • LATQ • TFMOD Set CxF Detector Counter Capture Register Holding Register Interrupt |
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