PC312XDP512F0CFVR datasheet(407/1348 Pages) FREESCALE

407 / 1348 page

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

407

from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when

its internal clocks are stopped.

If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal

clocks and interface would remain alive, continuing the operation which was currently underway. It is also

possible to conﬁgure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the

current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively.

9.3.2.4

IIC Status Register (IBSR)

This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software

clearable.

76543210

TCF

IAAS

IBB

IBAL

0SRW

IBIF

RXAK

Reset

10000000

= Unimplemented or Reserved

Figure 9-7. IIC Bus Status Register (IBSR)

Table 9-7. IBSR Field Descriptions

Field

Description

TCF

Data Transferring Bit — While one byte of data is being transferred, this bit is cleared. It is set by the falling

edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer

to the IIC module or from the IIC module.

0 Transfer in progress

1 Transfer complete

IAAS

Addressed as a Slave Bit — When its own speciﬁc address (I-bus address register) is matched with the calling

address, this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW

bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit.

0 Not addressed

1 Addressed as a slave

IBB

Bus Busy Bit

0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is

detected, IBB is cleared and the bus enters idle state.

1 Bus is busy

IBAL

Arbitration Lost — The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost.

Arbitration is lost in the following circumstances:

1. SDA sampled low when the master drives a high during an address or data transmit cycle.

2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle.

3. A start cycle is attempted when the bus is busy.

4. A repeated start cycle is requested in slave mode.

5. A stop condition is detected when the master did not request it.

This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit.

RESERVED

Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0.

PC312XDP512F0CFVR Datasheet(PDF) 407 Page - Freescale Semiconductor, Inc

PC312XDP512F0CFVR Datasheet(HTML) 407 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL