PC312XDP512F0CFVR datasheet(408/1348 Pages) FREESCALE

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

408

Freescale Semiconductor

9.3.2.5

IIC Data I/O Register (IBDR)

In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most signiﬁcant

bit is sent ﬁrst. In master receive mode, reading this register initiates next byte data receiving. In slave

mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the

IBCR must correctly reﬂect the desired direction of transfer in master and slave modes for the transmission

to begin. For instance, if the IIC is conﬁgured for master transmit but a master receive is desired, then

reading the IBDR will not initiate the receive.

Reading the IBDR will return the last byte received while the IIC is conﬁgured in either master receive or

slave receive modes. The IBDR does not reﬂect every byte that is transmitted on the IIC bus, nor can

software verify that a byte has been written to the IBDR correctly by reading it back.

In master transmit mode, the ﬁrst byte of data written to IBDR following assertion of MS/SL is used for

the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the

required R/W bit (in position D0).

SRW

Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address

sent from the master

This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address

match and no other transfers have been initiated.

Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master.

0 Slave receive, master writing to slave

1 Slave transmit, master reading from slave

IBIF

I-Bus Interrupt — The IBIF bit is set when one of the following conditions occurs:

— Arbitration lost (IBAL bit set)

— Byte transfer complete (TCF bit set)

— Addressed as slave (IAAS bit set)

It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one

to it. A write of 0 has no effect on this bit.

RXAK

Received Acknowledge — The value of SDA during the acknowledge bit of a bus cycle. If the received

acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8

bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock.

0 Acknowledge received

1 No acknowledge received

76543210

Reset

00000000

Figure 9-8. IIC Bus Data I/O Register (IBDR)

Table 9-7. IBSR Field Descriptions (continued)

Field

Description

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