PC312XDP512F0CFVR datasheet(412/1348 Pages) FREESCALE

412 / 1348 page

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

412

Freescale Semiconductor

Figure 9-11. IIC-Bus Clock Synchronization

9.4.1.8

Handshaking

The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold

the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces

the master clock into wait states until the slave releases the SCL line.

9.4.1.9

Clock Stretching

The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After

the master has driven SCL low the slave can drive SCL low for the required period and then release it.If

the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low

period is stretched.

9.4.2

Operation in Run Mode

This is the basic mode of operation.

9.4.3

Operation in Wait Mode

IIC operation in wait mode can be conﬁgured. Depending on the state of internal bits, the IIC can operate

normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module

enters a power conservation state during wait mode. In the later case, any transmission or reception in

progress stops at wait mode entry.

9.4.4

Operation in Stop Mode

The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC

SCL1

SCL2

SCL

Internal Counter Reset

WAIT

Start Counting High Period

PC312XDP512F0CFVR Datasheet(PDF) 412 Page - Freescale Semiconductor, Inc