PC312XDP512F0CFVR datasheet(424/1348 Pages) FREESCALE

424 / 1348 page

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

424

Freescale Semiconductor

10.3.2

This section describes in detail all the registers and register bits in the MSCAN module. Each description

includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld

function follow the register diagrams, in bit order. All bits of all registers in this module are completely

synchronous to internal clocks during a register read.

10.3.2.1

MSCAN Control Register 0 (CANCTL0)

The CANCTL0 register provides various control bits of the MSCAN module as described below.

NOTE

The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the

reset state when the initialization mode is active (INITRQ = 1 and

INITAK = 1). This register is writable again as soon as the initialization

mode is exited (INITRQ = 0 and INITAK = 0).

Read: Anytime

0x0014–0x0017

CANIDMRx

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

0x0018–0x001B

CANIDAR4–7

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

0x001C–0x001F

CANIDMR4–7

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

0x0020–0x002F

CANRXFG

See Section 10.3.3, “Programmer’s Model of Message Storage”

0x0030–0x003F

CANTXFG

See Section 10.3.3, “Programmer’s Model of Message Storage”

76543210

RXFRM

RXACT

CSWAI

SYNCH

TIME

WUPE

SLPRQ

INITRQ

Reset:

00000001

= Unimplemented

Figure 10-4. MSCAN Control Register 0 (CANCTL0)

Name

Bit 7

4321

Bit 0

= Unimplemented or Reserved

u = Unaffected

Figure 10-3. MSCAN Register Summary (continued)

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