PC312XDP512F0CFVR datasheet(498/1348 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

498

Freescale Semiconductor

The SCI also sets a ﬂag, the transmit data register empty ﬂag (TDRE), every time it transfers data from the

buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this ﬂag by

writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting

out the ﬁrst byte.

To initiate an SCI transmission:

1. Conﬁgure the SCI:

a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud

rate generator. Remember that the baud rate generator is disabled when the baud rate is zero.

Writing to the SCIBDH has no effect without also writing to SCIBDL.

b) Write to SCICR1 to conﬁgure word length, parity, and other conﬁguration bits

(LOOPS,RSRC,M,WAKE,ILT,PE,PT).

c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2

be shifted out of the transmitter shift register.

2. Transmit Procedure for each byte:

a) Poll the TDRE ﬂag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind

that the TDRE bit resets to one.

b) If the TDRE ﬂag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is

written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not

result until the TDRE ﬂag has been cleared.

3. Repeat step 2 for each subsequent transmission.

NOTE

The TDRE ﬂag is set when the shift register is loaded with the next data to

be transmitted from SCIDRH/L, which happens, generally speaking, a little

over half-way through the stop bit of the previous frame. Speciﬁcally, this

transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the

previous frame.

Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic

1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from

the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least

signiﬁcant bit position of the transmit shift register. A logic 1 stop bit goes into the most signiﬁcant bit

position.

Hardware supports odd or even parity. When parity is enabled, the most signiﬁcant bit (MSB) of the data

character is the parity bit.

The transmit data register empty ﬂag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI

data register transfers a byte to the transmit shift register. The TDRE ﬂag indicates that the SCI data

control register 2 (SCICR2) is also set, the TDRE ﬂag generates a transmitter interrupt request.

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