PC312XDP512F0CFVR datasheet(508/1348 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

508

Freescale Semiconductor

11.4.6.5

Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated

bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside

the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical

values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the

RT8, RT9, and RT10 stop bit samples are a logic zero.

As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge

within the frame. Re synchronization within frames will correct a misalignment between transmitter bit

times and receiver bit times.

11.4.6.5.1

Slow Data Tolerance

Figure 11-28 shows how much a slow received frame can be misaligned without causing a noise error or

a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data

samples at RT8, RT9, and RT10.

Figure 11-28. Slow Data

Let’s take RTr as receiver RT clock and RTt as transmitter RT clock.

For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles

to start data sampling of the stop bit.

With the misaligned character shown in Figure 11-28, the receiver counts 151 RTr cycles at the point when

the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data

character with no errors is:

((151 – 144) / 151) x 100 = 4.63%

For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles

to start data sampling of the stop bit.

With the misaligned character shown in Figure 11-28, the receiver counts 167 RTr cycles at the point when

the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit

character with no errors is:

((167 – 160) / 167) X 100 = 4.19%

MSB

Stop

Data

Samples

Receiver

RT Clock

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