PC312XDP512F0CFVR datasheet(512/1348 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

512

Freescale Semiconductor

11.5.2.2

Wait Mode

SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1

(SCICR1).

•

If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.

•

If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation

state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver

enable bit, RE, or the transmitter enable bit, TE.

If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The

transmission or reception resumes when either an internal or external interrupt brings the CPU out

of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and

resets the SCI.

11.5.2.3

Stop Mode

The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not

affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from

where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset

aborts any transmission or reception in progress and resets the SCI.

The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input

can be used to bring the CPU out of stop mode.

11.5.3

Interrupt Operation

This section describes the interrupt originated by the SCI block.The MCU must service the interrupt

requests. Table 11-19 lists the eight interrupt sources of the SCI.

Table 11-19. SCI Interrupt Sources

Interrupt

Source

Local Enable

Description

TDRE

SCISR1[7]

TIE

Active high level. Indicates that a byte was transferred from SCIDRH/L to the

transmit shift register.

SCISR1[6]

TCIE

Active high level. Indicates that a transmit is complete.

RDRF

SCISR1[5]

RIE

Active high level. The RDRF interrupt indicates that received data is available

in the SCI data register.

SCISR1[3]

Active high level. This interrupt indicates that an overrun condition has occurred.

IDLE

SCISR1[4]

ILIE

Active high level. Indicates that receiver input has become idle.

RXEDGIF

SCIASR1[7]

RXEDGIE

Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for

RXPOL = 1) was detected.

BERRIF

SCIASR1[1]

BERRIE

Active high level. Indicates that a mismatch between transmitted and received data

in a single wire application has happened.

BKDIF

SCIASR1[0]

BRKDIE

Active high level. Indicates that a break character has been received.

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