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PC312XDP512F0CFVR Datasheet(PDF) 570 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Datasheet(HTML) 570 Page - Freescale Semiconductor, Inc |
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570 / 1348 page  Chapter 15 Background Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 570 Freescale Semiconductor • Software control of BDM operation during wait mode • Software selectable clocks • Global page access functionality • Enabled but not active out of reset in emulation modes • CLKSW bit set out of reset in emulation mode. • When secured, hardware commands are allowed to access the register space in special single chip mode, if the Flash and EEPROM erase tests fail. • Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices is 0xC1) • BDM hardware commands are operational until system stop mode is entered (all bus masters are in stop mode) 15.1.2 Modes of Operation BDM is available in all operating modes but must be enabled before firmware commands are executed. Some systems may have a control bit that allows suspending the function during background debug mode. 15.1.2.1 Regular Run Modes All of these operations refer to the part in run mode and not being secured. The BDM does not provide controls to conserve power during run mode. • Normal modes General operation of the BDM is available and operates the same in all normal modes. • Special single chip mode In special single chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory. • Emulation modes In emulation mode, background operation is enabled but not active out of reset. This allows debugging and programming a system in this mode more easily. 15.1.2.2 Secure Mode Operation If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to Flash or EEPROM other than allowing erasure. For more information please see Section 15.4.1, “Security”. |
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