PC312XDP512F0CFVR datasheet(609/1348 Pages) FREESCALE

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Chapter 16 Interrupt (S12XINTV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

609

If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive

after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the

CPU will default to that of the spurious interrupt vector.

NOTE

Care must be taken to ensure that all exception requests remain active until

the system begins execution of the applicable service routine; otherwise, the

exception request may not get processed at all or the result may be a

spurious interrupt request (vector at address (vector base + 0x0010)).

16.4.5

Reset Exception Requests

The XINT supports three system reset exception request types (please refer to CRG for details):

1. Pin reset, power-on reset, low-voltage reset, or illegal address reset

2. Clock monitor reset request

3. COP watchdog reset request

16.4.6

Exception Priority

The priority (from highest to lowest) and address of all exception vectors issued by the XINT upon request

by the CPU is shown in Table 16-8.

Table 16-8. Exception Vector Map and Priority

Vector Address1

1 16 bits vector address based

Source

0xFFFE

Pin reset, power-on reset, low-voltage reset, illegal address reset

0xFFFC

Clock monitor reset

0xFFFA

COP watchdog reset

(Vector base + 0x00F8)

Unimplemented opcode trap

(Vector base + 0x00F6)

Software interrupt instruction (SWI) or BDM vector request

(Vector base + 0x00F4)

XIRQ interrupt request

(Vector base + 0x00F2)

IRQ interrupt request

(Vector base + 0x00F0–0x0012) Device speciﬁc I bit maskable interrupt sources (priority determined by the associated

conﬁguration registers, in descending order)

(Vector base + 0x0010)

Spurious interrupt

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