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PC312XDP512F0CFVR Datasheet(PDF) 653 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Datasheet(HTML) 653 Page - Freescale Semiconductor, Inc |
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653 / 1348 page  Chapter 18 Memory Mapping Control (S12XMMCV3) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 653 • Simultaneous accesses to different resources1 (internal, external, and peripherals) (see ) • Resolution of target bus access collision • Access restriction control from masters to some targets (e.g., RAM write access protection for user specified areas) • MCU operation mode control • MCU security control • Separate memory map schemes for each master CPU, BDM and XGATE • ROM control bits to enable the on-chip FLASH or ROM selection • Port replacement registers access control • Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes 18.1.3 S12X Memory Mapping The S12X architecture implements a number of memory mapping schemes including • a CPU 8 MByte global map, defined using a global page (GPAGE) register and dedicated 23-bit address load/store instructions. • a BDM 8 MByte global map, defined using a global page (BDMGPR) register and dedicated 23-bit address load/store instructions. • a (CPU or BDM) 64 KByte local map, defined using specific resource page (RPAGE, EPAGE and PPAGE) registers and the default instruction set. The 64 KBytes visible at any instant can be considered as the local map accessed by the 16-bit (CPU or BDM) address. • The XGATE 64 Kbyte local map. The MMC module performs translation of the different memory mapping schemes to the specific global (physical) memory implementation. 18.1.4 Modes of Operation This subsection lists and briefly describes all operating modes supported by the MMC. 18.1.4.1 Power Saving Modes • Run mode MMC is functional during normal run mode. • Wait mode MMC is functional during wait mode. • Stop mode MMC is inactive during stop mode. 1. Resources are also called targets. |
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